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REF: BB_SRM_xM BeagleBoard-xM System
Reference Manual
Revision A2
Page 97 of 164
8.20.1 Camera Power
There are three main power sources required by the camera module. Each of these are
described in the following sections.
8.20.1.1 CAM_ANA Power
The DC input can be either 5V or 3.3V. It is selected by installing either R151 or R154.
The default is set at 3.3V and is controlled by turning on and off the USB HUB power
rail at U16. The power is controlled by setting the LEDA signal on the TPS65950.
Access to this register is via the I2C2 interface on the processor.
The 5V is on whenever a power source is applied o the board.
8.20.1.2 CAM_DIGITAL Power
The digital power is a 1.8V rail that is supplied by the TPS65950. The power is
controlled via the I2C1 interface from the processor by setting the VAUX4 regulator to
1.8V. This is used for the internal logic in the camera module.
8.20.1.3 CAM_IO Power
The I/O power is a 1.8V rail that is supplied by the TPS65950. The power is controlled
via the I2C1 interface from the processor by setting the VAUX3 regulator to 1.8V. This
will set the level of all of the interface signals to the processor.
8.20.2 Camera I2C Port
The processor uses the I2C2 port to communicate to the camera module to set the
registers in the device. There are no pullups on the board for the I2C to prevent conflict
with add on boards that do have the pullups. If an add-on board is not used, the SW will
need to enable the internal pullups on the I2C2 signals in order for the interface to work.
8.20.3 Processor Camera Port Interface
Table 19 shows the signals that are the interface between the processor and the camera
modules. The I/O status of each pin is defined from the perspective of the processor.
The cam_wen signal is labeled as CMOS_OE on the schematic. All of the current
camera modules do not use this signal and this signal has no affect on the operation of the
camera modules. It is provided for future use.
- BeagleBoard-xM Rev A2 1
- System Reference Manual 1
- Table of Contents 5
- Figures 9
- Tables 11
- 1.0 Introduction 13
- 2.0 Change History 15
- 2.2.2 Software Changes 16
- 4.0 BeagleBoard Overview 17
- Figure 2. USB Y-Cable 21
- 6.0 Product Contents 28
- 7.0 BeagleBoard Hookup 30
- BEAGLEBOARD 36
- VOLT_ERR 45
- 8.2.1 Detection 46
- 8.2.2 Indication 46
- 8.2.3 Shutdown 46
- USB_CLIENT / 47
- OTG PORT 47
- DC_POWER 47
- 8.3.1 USB DC Source 48
- 8.3.2 Wall Supply Source 48
- 8.3.3 DC Source Control 48
- 8.3.4 AUX 3.3V Supply 49
- Figure 25. Main Power Rails 55
- 8.7.6 VOCORE_1V3 56
- 8.7.7 VDD2 56
- 8.8.1 VDD_PLL2 57
- 8.8.2 VDD_PLL1 58
- 8.8.3 VDAC_1V8 58
- 8.8.10 EXP_VDD 60
- 8.9.1 Boot Configuration 60
- 8.9.2 RTC Backup Battery 60
- 8.9.3 Power Sequencing 61
- Figure 27. Power Sequencing 61
- 8.9.4.3 User Reset 63
- 8.9.4.4 PWRON 63
- 8.9.5 mSecure Signal 63
- 8.10.1 Overview 64
- 8.10.2 SDRAM Bus 65
- 8.10.3 GPMC Bus 65
- Processor 66
- 8.10.9 GPIO Mapping 69
- 8.10.10 Interrupt Mapping 69
- Figure 33. POP Memory 70
- Figure 34. System Clocks 70
- 8.12.1 32KHz Clock 71
- 8.12.2 26MHz Clock 71
- 8.12.2.1 26MHz Source 71
- 8.12.2.2 TPS65950 Setup 71
- 8.12.2.3 Processor 26MHz 71
- 8.12.3 McBSP_CLKS 72
- 8.13.1 USB OTG Overview 72
- 8.13.2 USB OTG Design 73
- Figure 35. USB OTG Design 73
- 8.13.3 OTG ULPI Interface 73
- 8.13.3.2 TPS65950 Interface 74
- 8.13.4 OTG Charge Pump 74
- 8.13.5 OTG USB Connector 75
- 8.13.6 OTG USB Protection 75
- 8.14.1 Power 76
- 8.14.2 HS USB PHY 77
- Figure 38. USB PHY Design 78
- 8.14.3 USB HUB 79
- Figure 39. USB HUB Design 80
- 8.14.4 USB Port Connectors 81
- 8.14.5 Ethernet 82
- 8.15.1 microSD Power 83
- 8.15.2 Processor Interface 83
- 8.15.3 Card Detect 84
- Figure 43. Audio Circuitry 85
- 8.16.3 Audio Output Jack 86
- 8.16.4 Audio Input Jack 86
- Figure 44. DVI-D Interface 87
- 8.17.2 LCD Power 89
- 8.17.3 TFP410 Power 89
- 8.17.4 TFP410 Framer 89
- 8.17.6.8 DVI to VGA 93
- Table 16. P11 LCD Signals 93
- Table 17. P13 LCD Signals 94
- 8.20.4 Camera Modules 100
- Figure 47. Camera Modules 100
- 8.21.1 Processor Interface 101
- 8.21.2 Level Translator 101
- 8.21.3 RS232 Transceiver 102
- 8.21.4 Connector 102
- 8.22.1 Power Indicator 103
- 8.22.2 PMU Status Indicator 103
- Figure 49. Indicator Design 103
- 8.22.3 User Indicators 104
- 8.22.4 HUB Power Indicator 104
- Figure 50. JTAG Interface 105
- 8.23.1 Processor Interface 105
- Table 21. JTAG Signals 105
- 8.23.2 JTAG Connector 106
- 8.24.1 Processor Interface 106
- 8.24.2 Expansion Signals 108
- 8.24.3 Power 109
- 8.24.4 Reset 109
- 8.24.5 Power Control 109
- Table 24. P11 GPIO Signals 110
- MUX:0 MUX:2 MUX:4 110
- Table 25. P13 GPIO Signals 110
- 8.26.1 MCBSP5 Signals 111
- 8.26.2 MMC3 Signals 112
- 8.26.3 ETK Signals 112
- 8.26.4 HSUSB1 Signals 113
- 8.26.5 Alternate Clock 113
- 8.26.6 HDQ 1-Wire 113
- 8.26.7 ADC 113
- 8.26.8 GPIO Signals 114
- 8.26.9 DMAREQ 114
- Figure 52. Power Connector 115
- Figure 56. DVI-D Connector 118
- DVI-D interface itself 118
- Figure 57. DVI-D Cable 119
- Figure 58. DVI-D Cable 119
- 9.5.1 Connector Pinout 120
- Table 33. P11 LCD Signals 120
- Table 34. P13 LCD Signals 121
- 9.5.2 Camera 122
- Figure 60. Camera Connector 123
- Figure 61. Camera Module 123
- 9.5.3 Audio McBSP2 Port 124
- 9.5.6 Mounting Scenarios 127
- Figure 66. Audio In Plug 128
- Figure 68. Audio Out Plug 129
- Table 39. JTAG Signals 130
- 9.9.1 Battery 132
- Figure 73. Optional Battery 132
- 9.9.2 Battery Installation 132
- Figure 75. Resistor R65 133
- Table 41. DC Power Supplies 135
- Figure 76. DC Power Supply 135
- Figure 79. USB to Bluetooth 138
- 11.0 Mechanical Information 140
- 11.2.1 Mounting Method 141
- 11.2.2 Expansion EEPROM 143
- Table 46. Voltages 145
- 12.1.1 Signal Access Points 146
- Table 47. Troubleshooting 147
- 13.0 Known Issues 148
- 15.0 Schematics 151
- 16.0 Bills of Material 163
- 17.0 PCB Information 164
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